The present invention relates, in general, to non-volatile memory devices, and more particularly to a memory cell incorporating a single polysilicon floating gate structure.
Electrically Erasable Programmable Read Only Memories (EEPROM's) are well known and well used in the art. They provide a method for storing data that can be retained even if power to the memory is removed. Most EEPROM's store charge on an electrically isolated floating gate which is used to control the state of a single transistor. The two focal points of EEPROM designs involve how to place a voltage potential on an isolated floating gate and how to determine the state of the single transistor.
There are two common approaches for isolating a floating gate structure and capacitively coupling the floating gate so it can be programmed or erased. The first approach uses a double dielectric/conductor stack to form a floating gate between two dielectric layers which is controlled by a second conductor referred to as a control gate. The control gate is used to place a voltage potential on the floating gate to control movement of charge to and from the floating gate. When the voltage is removed from the control gate, the trapped charge will remain to provide a stored voltage potential in the memory cell. The structure requires the formation of two conductive layers which is typically accomplished with two polysilicon depositions.
The second approach for isolating a floating gate structure uses a single polysilicon layer to form a capacitor to the substrate. One portion of the capacitor is the isolated gate of a single transistor and is used to provide the programming voltage on the isolated gate. The capacitor electrically separates the isolated gate from the rest of the circuit and controls the movement of electrons to and from the isolated gate through the dielectric layer of the capacitor.
To determine the state of the single transistor, we need to determine if the transistor is conducting at one of two levels. Typically if the transistor is `on` this is to be interpreted as a logic `1` and if the transistor is off a logic `0` is assumed or vice versa. Such techniques rely on sense amp circuitry to determine which logic level the current of the read transistor implies. Then once the logic condition is determined by the sense amp, a read voltage must be generated to serve as the output of the memory cell.
With most EEPROM designs, the above mentioned considerations add complexity to traditional CMOS process and design procedures. Additional process steps are required to form the double polysilicon stack or complications may arise with the addition of high voltage potentials for EEPROM's in close proximity to traditional CMOS devices. The addition of sense amp and read voltage circuitry will also consume valuable layout space which will increase the cost of the final product.
Accordingly, it would be advantageous to provide a structure for a non-volatile memory cell which can be constructed from a single polysilicon deposition such that the floating gate structure can be formed during the same process steps that form the gate structures for common CMOS devices. It would be of further advantage to form an EEPROM cell which is capable of generating a read voltage that does not require the use of sense amp or buffer circuitry and could be formed using the traditional constraints of a CMOS process flow without any additional process steps.